----------------------------------------------------
--  
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  RSTGEN
--      Library Name :  utils
--  
--  Creation Date    :  Sat Aug 14 21:41:12 1999
--  Version          :  v5.2.7 from 29-Nov-1998
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  No
--         Code Destination     :  Combined File
--         Case for Names       :  
--         Attach Packages      :  No
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  utils
--  Unit    Name :  RSTGEN
--  Unit    Type :  Text Unit
--  
------------------------------------------------------
----------------------------------------------------
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  RSTGEN
--      Library Name :  project
--  
--  Creation Date    :  Thu Aug 20 12:16:14 1998
--  Version          :  v4.0.2
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  As Needed
--         Code Destination     :  Combined File
--         Case for Names       :  Lower
--         Attach Packages      :  Yes
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--  
----------------------------------------------------------------------------------
---- Copyright (c) 1996, ASM Lithography
----------------------------------------------------------------------------------
---- Purpose      : 
----
----------------------------------------------------------------------------------
---- Comment      : 
----
----------------------------------------------------------------------------------
---- Assumptions  : 
----
----------------------------------------------------------------------------------
---- Limitations  : 
----
----------------------------------------------------------------------------------
---- Known errors : 
----
----------------------------------------------------------------------------------
---- Specification reference : 
----
----------------------------------------------------------------------------------
----
---- History List
---- Date         Release            Author             Comment
---- 09-Jul-1998  First release    G.J. Tromp
----
----------------------------------------------------------------------------------
--  
----------------------------------------------------

----------------------------------------------------
--  
--  Library Name :  project
--  Unit    Name :  RSTGEN
--  Unit    Type :  Text Unit
--  
----------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity rstgen is

generic (
   Reset_Active: std_logic := '0';
   Reset_Duration: time := 256 ns
);

port (
   reset: out std_logic
);

end rstgen;

architecture behv of rstgen is

signal reset_v: std_logic := Reset_Active;

begin

reset_v <= not Reset_Active after Reset_Duration;

reset <= reset_v;

end;