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--  
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  i2s_dec
--      Library Name :  i2s
--  
--  Creation Date    :  Sat Aug 14 21:30:43 1999
--  Version          :  v5.2.7 from 29-Nov-1998
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  No
--         Code Destination     :  Combined File
--         Case for Names       :  
--         Attach Packages      :  No
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  i2s
--  Unit    Name :  i2s_dec
--  Unit    Type :  Text Unit
--  
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-- Date        : Fri Aug 13 23:47:43 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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library ieee; use ieee.std_logic_1164.all;

entity  i2s_dec  is
port (scli : in std_logic ;
      wci : in std_logic ;
      sdi : in std_logic ;
      clk : in std_logic ;
      reset : in std_logic ;
      Left_Channel : out std_logic_vector(23 downto 0) ;
      Right_Channel : out std_logic_vector(23 downto 0) ;
      Left_Clock : out std_logic ;
      Right_Clock : out std_logic );
end;
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-- Date        : Fri Aug 13 23:47:43 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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architecture  behavioral  of  i2s_dec  is

signal scli_c, sdi_c, wci_c: std_logic;
signal scli_d, wci_d: std_logic;
signal shift_reg: std_logic_vector(23 downto 0);

begin
--
-- Make signals clock synchronous
--
Clock_Process: process(clk)

begin
   if rising_edge(clk) then
      scli_c <= scli;
      sdi_c <= sdi;
      wci_c <= wci;
      scli_d <= scli_c;
      wci_d <= wci_c;
   end if;
end process;

Shift_Process: process(reset, clk)

begin
   if reset = '0' then
      Left_Channel <= (others => '0');
      Right_Channel <= (others => '0');
      Left_Clock <= '0';
      Right_Clock <= '0';
      Shift_Reg <= (others => '0');
   elsif rising_edge(clk) then
--
-- On rising edge of scli, shift in the data
--
      if scli_d = '0' and scli_c = '1' then
         Shift_Reg(0) <= sdi_c;
         Shift_Reg(23 downto 1) <= Shift_Reg(22 downto 0);
      end if;
--
-- On rising edge of wci, store the data in the
-- shift register in the Left_Channel
--
      if wci_d = '0' and wci_c = '1' then
         Left_Channel <= Shift_Reg;
         Left_Clock <= '1';
         Right_clock <= '0';
--
-- On falling edge of wci, store the data in the
-- shift register in the Right_Channel
--
      elsif wci_d = '1' and wci_c = '0' then
         Right_Channel <= Shift_Reg;
         Left_Clock <= '0';
         Right_clock <= '1';
      end if;
   end if;
end process;


end;