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--  
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  Gen
--      Library Name :  i2s
--  
--  Creation Date    :  Sat Aug 14 21:41:57 1999
--  Version          :  v5.2.7 from 29-Nov-1998
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  No
--         Code Destination     :  Combined File
--         Case for Names       :  
--         Attach Packages      :  No
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  i2s
--  Unit    Name :  Gen
--  Unit    Type :  Text Unit
--  
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-- Date        : Fri Aug 13 23:43:35 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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library ieee; use ieee.std_logic_1164.all;

entity  Gen  is

generic (
   width: integer range 4 to 32
);
port (cycle : out BOOLEAN ;
      scli : in std_logic ;
      stream : in std_logic_vector (width - 1 downto 0);
      sdi : out std_logic );
end;


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-- Date        : Fri Aug 13 23:43:35 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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architecture  behavioral  of  Gen  is
begin

cycle <= (scli = '1');
sdi <= stream(11);

end;