----------------------------------------------------
--  
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  CLKGEN
--      Library Name :  utils
--  
--  Creation Date    :  Sat Aug 14 21:40:52 1999
--  Version          :  v5.2.7 from 29-Nov-1998
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  No
--         Code Destination     :  Combined File
--         Case for Names       :  
--         Attach Packages      :  No
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  utils
--  Unit    Name :  CLKGEN
--  Unit    Type :  Text Unit
--  
------------------------------------------------------


--------------------------------------------------------------------------------
-- Copyright (c) 1996, ASM Lithography
--------------------------------------------------------------------------------
--
-- Title        : 
-- Filename     :
-- Contents     : 
--
-- 
--------------------------------------------------------------------------------
-- Author(s)    : 
--
--------------------------------------------------------------------------------
-- VHDL Style   : 87/93
--------------------------------------------------------------------------------
-- Purpose      : Clock generator simulation model
--
--------------------------------------------------------------------------------
-- Comment      : 
--
--------------------------------------------------------------------------------
-- Assumptions  : 
--
--------------------------------------------------------------------------------
-- Limitations  : 
--
--------------------------------------------------------------------------------
-- Known errors : 
--
--------------------------------------------------------------------------------
-- Specification reference : 
--
--------------------------------------------------------------------------------
--
-- History List
-- Date         Release            Author             Comment
-- 14-Jul-1998  First release   G.J. Tromp
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity clkgen is

generic (
   Low_Period:    time := 12500 ps;
   High_Period:   time := 12500 ps;
   Initial_Delay: time := 0 ps
);

port (
   clk: out std_logic
);

end clkgen;
architecture behv of clkgen is

signal clk_v: std_logic;

begin

process

variable c: std_logic := '0';
variable init: boolean := TRUE;

begin
   if init then
      wait for Initial_Delay;

      init := FALSE;
   end if;

   clk_v <= c after Low_Period;

   wait on clk_v;

   c := not c;

   clk_v <= c after High_Period;

   wait on clk_v;

   c := not c;
   
end process;

clk <= clk_v;

end;