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--  
--  
--      VHDL code generated by Visual HDL
--
--  Root of Design:
--  ---------------
--      Unit    Name :  CA_Random_Gen
--      Library Name :  car
--  
--  Creation Date    :  Sat Aug 14 21:30:00 1999
--  Version          :  v5.2.7 from 29-Nov-1998
--  
--  Options Used:
--  -------------
--      Target    :  
--         HDL    :  VHDL
--         Purpose:  Simulation
--         Vendor :    ---  
--  
--      Style:   
--         Use Procedures       :  No
--         Code Destination     :  Combined File
--         Case for Names       :  
--         Attach Packages      :  No
--         Generate Entity      :  Yes
--         Attach Directives    :  Yes
--         Structural           :  No
--
----------------------------------------------------
----------------------------------------------------
--  
--  Library Name :  car
--  Unit    Name :  CA_Random_Gen
--  Unit    Type :  Text Unit
--  
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-- Date        : Mon Aug 09 11:33:30 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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library ieee;
use ieee.std_logic_1164.all;

entity  CA_Random_Gen  is

generic (
   width: integer range 4 to 32;
   seed: std_logic_vector(31 downto 0) := (others => '1');
   cyclic: boolean := FALSE;
   left: std_logic := '0';
   right: std_logic := '0'
);
port (stream : out std_logic_vector(width -1 downto 0) ;
      cycle : in boolean );
end;

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-- Date        : Mon Aug 09 11:33:30 1999
--
-- Author      : 
--
-- Company     : 
--
-- Description : 
--
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architecture  behavioral  of  CA_Random_Gen  is

type Construction_Rule_Array is array (4 to 32) of
   std_logic_vector(31 downto 0);

constant Construction_Rules: Construction_Rule_Array := (
   4 => "00000000000000000000000000000101",
  12 => "00000000000000000000010101010101", 
  16 => "00000000000000001101010101010101",
  24 => "00000000111111010010110101010110",
  26 => "00000001011010110100010111011000", 
  32 => "00011111100100011001110110110000",
   others => (others => '0')
);

constant Construction_Rule: std_logic_vector(width -1 downto 0) :=
   Construction_Rules(width)(width -1 downto 0);

signal ca: std_logic_vector(width -1 downto 0) := seed(width -1 downto 0);

begin

CAR_Process: process

begin
--
-- left and  right cells are exceptions
-- if cyclic then use the most right cell as
-- the left neighbour of the most left cell and the
-- most left cell as the right neighbour of the
-- most right cell, otherwise use the left and right
-- (generic) values
--
   if cyclic then
      if Construction_Rule(0) = '1' then
         ca(0) <= ca(0) xor ca(width-1) xor ca(1);
      else
         ca(0) <= ca(width-1) xor ca(1);
      end if;
      if Construction_Rule(width-1) = '1' then
         ca(width-1) <= ca(width-1) xor ca(width-2) xor ca(0);
      else
         ca(width-1) <= ca(width-2) xor ca(0);
      end if;
   else
      if Construction_Rule(0) = '1' then
         ca(0) <= ca(0) xor right xor ca(1);
      else
         ca(0) <= right xor ca(1);
      end if;
      if Construction_Rule(width-1) = '1' then
         ca(width-1) <= ca(width-1) xor ca(width-2) xor left;
      else
         ca(width-1) <= ca(width-2) xor left;
      end if;
   end if;

-- Do other cells

   for i in 1 to width -2 loop
      if Construction_Rule(i) = '1' then
         ca(i) <= ca(i) xor ca(i-1) xor ca(i+1);
      else
         ca(i) <= ca(i-1) xor ca(i+1);
      end if;
   end loop;

   wait until cycle;

end process;

stream <= ca;

end;